Verisense Hardware Verification Platforms
Hardware verification is one of the most crucial phases to the DO-254 process since this is where the design is checked vs. the initial formal requirements. As such, an efficient mechanism to link the verification plan and its results back to the original requirements documents is mandatory for demonstrating DO-254 compliance.
However for FPGA and ASICs, this is also the area which is most lacking in verification tools and there is no de-facto industry-wide accepted practice on what is the most appropriate method for hardware verification. It is important to note that DO-254 specifies a process but it does not specify the detailed implementation of the process.
Historically, the most common method for hardware verification was to probe the pins of the FPGA. This is a very time consuming process which is often very complex, not automated, not easily reproducible, and often not really technologically feasible, especially on high speed interfaces.
The Verisense hardware verification tester tool platforms close this gap!
The two most common approaches to hardware verification of FPGAs and ASICs are either dedicated hardware in the loop testers in which you test the FPGA or ASIC in a dedicated system designed specifically for this purpose, or verification of the FPGA/ASIC in the final destination hardware system.
Verisense has developed hardware verification tester tools to address both these approaches. They are already being used to certify customer DAL A and B FPGA designs. We would be happy to discuss your needs and our solutions with you.
It is important to note that the eventual complexity (and cost) of the hardware verification solution can often be substantially reduced by making fairly simple decisions in the definition stage of your product. We strongly suggest that you be in touch with us as early in your development process as possible.
See our product brief.